1. Field of the Invention
The present invention relates to a method of operating a flash memory device, and more particularly, to a method of operating a flash memory device that is capable of readily controlling the threshold voltages of a string selection transistor and a ground selection transistor.
This application claims priority to Korean Patent Application No. 2004-93845, filed on Nov. 17, 2004, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
In general, flash memory devices are non-volatile memory devices, and have been widely used in digital cameras, computers, mobile phones, memory cards, etc. Each flash memory device can be classified as either a NOR flash memory device or a NAND flash memory device.
It is difficult to integrate NOR flash memory devices because a contact hole must be formed in the source/drain region of each constituent cell transistor. In contrast, however, it is relatively easy to integrate NAND flash memory devices which in conventional form include a string structure comprising a plurality of series connected cell transistors.
Each string structure of a NAND flash memory device also comprises a connected combination of a string selection transistor and a ground selection transistor. In contrast to the cell transistors forming the data storage mechanism on the NAND flash memory device which typically comprise a tunnel oxide layer, a floating gate electrode formed on the tunnel oxide layer, a dielectric layer formed on the floating gate electrode, and a control gate electrode formed on the dielectric layer, the string selection and ground selection transistors each comprise a tunnel oxide layer and a gate electrode formed on the tunnel oxide layer.
A cell transistor in a NAND flash memory device stores data in accordance with its threshold voltage. That is, electrical charge developed on the floating gate electrode of the cell transistor establishes the threshold voltage of the cell transistor. The threshold voltage indicates a logic state for the cell transistor as it varies between a program state and an erase state. Conventionally, the erase state has a relatively low threshold voltage and represents a logically low data bit value of “0,” while the program state has a relatively high threshold voltage and represents a logically high data bit data value of “1.”
When operating a NAND flash memory device, the respective threshold voltages of the cell transistors may be readily (i.e., easily or conveniently) controlled, since the cell transistors each comprise a floating gate electrode or a dielectric layer capable of trapping electrical charge. However, since the string selection transistor and the ground selection transistor each comprise but a single gate electrode without a floating gate electrode or a dielectric layer, the respective threshold voltages of the string selection and ground selection transistors are not readily controllable. Thus, a NAND flash memory device comprising the string selection transistor and the ground selection transistor tends to malfunction frequently. Particularly, when the threshold voltages of the string selection transistor and the ground selection transistor are low, the string selection transistor and the ground selection transistor undesirably turn on, so the NAND flash memory device tends to malfunction frequently.
In order to control the respective threshold voltages of the string selection and ground selection transistors, and thus suppress the malfunctioning problem inherent in these type of NAND flash memory devices, impurities are selectively implanted (i.e., implanted using conventional ion implantation techniques) into a substrate region in which the string selection and ground selection transistors are formed.
However, since the ion implantation process constitutes an additional fabrication step, otherwise unneeded in the formation of the NAND flash memory device cell transistors, and since the ion implantation is conventionally performed on a substrate region in which the string selection and ground selection transistors are formed, the conventional remediation scheme addressing the malfunctioning problem inhibits the integration of conventional NAND flash memory devices. As a result, the threshold voltages associated with the string selection and ground selection transistors are not readily controllable, so the conventional NAND flash memory device has inferior electrical reliability.